Feed: AnandTech
Feed Link: https://www.anandtech.com
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Title: PCIe 7.0 Draft 0.5 Spec Available: 512 GB/s over PCIe x16 On Track For
2025

Date: Thu, 04 Apr 2024 08:00:00 EDT
Link: https://www.anandtech.com/show/21335/full-dra...

PCI-SIG this week released version 0.5 of the PCI-Express 7.0 specification
to its members. This is the second draft of the spec and the final call for
PCI-SIG members to submit their new features to the standard. The latest
update on the development of the specification comes a couple months shy of a
year after the PCI-SIG published the initial Draft 0.3 specificaiton, with
the PCI-SIG using the latest update to reiterate that development of the new
standard remains on-track for a final release in 2025.

PCIe 7.0 is is the next generation interconnect technology for computers that
is set to increase data transfer speeds to 128 GT/s per pin, doubling the 64
GT/s of PCIe 6.0 and quadrupling the 32 GT/s of PCIe 5.0. This would allow a
16-lane (x16) connection to support 256 GB/sec of bandwidth in each direction
simultaneously, excluding encoding overhead. Such speeds will be handy for
future datacenters as well as artificial intelligence and high-performance
computing applications that will need even faster data transfer rates,
including network data transfer rates.

To achieve its impressive data transfer rates, PCIe 7.0 doubles the bus
frequency at the physical layer compared to PCIe 5.0 and 6.0. Otherwise, the
standard retains pulse amplitude modulation with four level signaling (PAM4),
1b/1b FLIT mode encoding, and the forward error correction (FEC) technologies
that are already used for PCIe 6.0. Otherwise, PCI-SIG says that the PCIe 7.0
speicification also focuses on enhanced channel parameters and reach as well
as improved power efficiency.

Overall, the engineers behind the standard have their work cut out for them,
given that PCIe 7.0 requires doubling the bus frequency at the physical
layer, a major development that PCIe 6.0 sidestepped with PAM4 signaling.
Nothing comes for free in regards to improving data signaling, and with PCIe
7.0, the PCI-SIG is arguably back to hard-mode development by needing to
improve the physical layer once more - this time to enable it to run at
around 30GHz. Though how much of this heavy lifting will be accomplished
through smart signaling (and retimers) and how much will be accomplished
through sheer materials improvements, such as thicker printed circuit boards
(PCBs) and low-loss materials, remains to be seen.

The next major step for PCIe 7.0 is finalization of the version 0.7 of
specification, which is considered the Complete Draft, where all aspects must
be fully defined, and electrical specifications must be validated through
test chips. After this iteration of the specification is released, no new
features can be added. PCIe 6.0 eventually went through 4 major drafts - 0.3,
0.5, 0.7, and 0.9 - before finally being finalized, so PCIe 7.0 is likely on
the same track.

Once finalized in 2025, it should take a few years for the first PCIe 7.0
hardware to hit the shelves. Although development work on controller IP and
initial hardware is already underway, that process extends well beyond the
release of the final PCIe specification.

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